--
-- VHDL Architecture Fietscomputer_lib.gen_multiplier.combi
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp7985)
--          at - 16:49:17  7-07-2010
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY fc_gen_multiplier IS
  GENERIC( 
  na : NATURAL := 12;
  nb : NATURAL := 12
  );
  PORT( 
  a     : IN     STD_LOGIC_VECTOR(49 DOWNTO 0);
  b     : IN     STD_LOGIC_VECTOR(49 DOWNTO 0) := (OTHERS => '0');
  p     : OUT    STD_LOGIC_VECTOR(49 DOWNTO 0);
  start : IN     STD_LOGIC;
  clk   : IN     STD_LOGIC;
  rst   : IN     STD_LOGIC;
  ready : OUT    STD_LOGIC
  );
  
  
END fc_gen_multiplier ;


ARCHITECTURE combi OF fc_gen_multiplier IS


SIGNAL areg : STD_LOGIC_VECTOR(   na-1 DOWNTO 0);
SIGNAL breg : STD_LOGIC_VECTOR(   nb-1 DOWNTO 0);
SIGNAL preg : STD_LOGIC_VECTOR(na+nb-1 DOWNTO 0);
SIGNAL cntr : NATURAL RANGE 0 TO 1;


BEGIN
  
  
  PROCESS(rst, clk)
    BEGIN
      IF rst = '1' THEN
        areg <= (OTHERS => '0');
        breg <= (OTHERS => '0');
        preg <= (OTHERS => '0');
        cntr <=  0;
        ready <= '0';
      ELSIF RISING_EDGE(clk) THEN
        
        IF start = '1' THEN
          areg <= a(na-1 DOWNTO 0);
          breg <= b(nb-1 DOWNTO 0);
          cntr <= 1;
        ELSIF cntr > 0 THEN
          preg <= areg * breg;
          cntr <= cntr - 1;
        END IF;  
        
        IF cntr = 1 THEN
          ready <= '1';
        ELSE
          ready <= '0';
        END IF;
        
      END IF;
    END PROCESS;
    
    
    p(na+nb-1 DOWNTO 0) <= preg;
    p(49 DOWNTO na+nb)  <= (OTHERS => '0');
    
  
   
    
  END ARCHITECTURE combi;
  
  
  
  
  